1. Field of the Disclosure
The present disclosure generally relates to methods of forming semiconductor device structures and semiconductor device structures, and, more particularly, to the fabrication of semiconductor device structures for higher voltage I/O applications and according semiconductor device structures used in higher voltage I/O applications.
2. Description of the Related Art
Efforts to integrate more and more semiconductor devices on a semiconductor chip, and, alternatively, to optimize power loss of integrated circuits, resulted in the fabrication of integrated circuits having circuit elements of critical dimensions reaching into the deep sub-micron regime, currently 22 nanometers and beyond. The downscaling of circuit elements, such as transistor elements, e.g., MOSFET devices, to advanced scales raised constraints and issues to be dealt with, such as short channel effects, tunneling leakage, dielectric breakdown, etc. For example, the scaling of MOSFET devices poses an upper limit on the possible thickness of a gate dielectric at which reliable control of a channel region below a gate electrode is still maintained. With decreasing MOSFET size, the thickness of silicon dioxide used as a gate dielectric has decreased in order to increase the gate capacitance, and thereby the drive current, wherein the conductance of the channel region is, for example, modulated by the gate dielectric sustaining a sufficient high electric field transverse to the channel, the electric field normally being in a range from 1-5 MV/cm. On the other hand, the scaling of the thickness of a gate dielectric to smaller thickness values imposes constraints on the allowed magnitude of the electric field, bounded by a value at which electric breakdown (that is, rapid reduction in the resistance) of the gate dielectric occurs. On the one hand, the permissible voltage applied to a gate electrode depends on the thickness of a gate dielectric separating channel and gate. On the other hand, voltage values encountered in certain applications set constraints on the thickness of the dielectric, among others.
Conventionally, transistor devices are distinguished regarding the thickness of the gate dielectric as follows: devices having a thin gate dielectric (e.g., a thickness up to about 20 Å, such as having a thickness of about 10 Å) are referred to as “SG devices,” devices having a normal gate dielectric (e.g., a thickness in a range from about 20-50 Å, such as having a thickness of about 35 Å) are referred to as “EG devices,” and devices having a relatively thick gate dielectric (e.g., a thickness in a range from about 50 Å on, such as having a thickness of about 66 Å) are referred to as “ZG devices.” The permissible voltage values, in which these devices may be operated, are as follows: SG devices may be operated between 0.6-1.2 V, EG devices may be operated in a range from about 1.2-1.8 V, and ZG devices may be operated above 1.8 V, commonly at 2.5 V and 3.3 V.
For example, SG devices, EG devices and ZG devices are used in I/O applications as I/O devices controlling the I/O voltage at I/O interfaces. For example, most current DDR SDRAM devices operate at a voltage of 2.5 volt, as compared to 3.3 volt for SDRAM, and thus, DDR SDRAM significantly reduces the power consumption over SDRAM. In further current variations of DDR SDRAM, the operating voltage is reduced from 2.5/2.6 V for DDR SDRAM, to 1.8 V for DDR2, to 1.5 V for DDR3, and even down to 1.05/1.2 V for DDR4. Accordingly, greater power efficiency has been achieved for DDR which is, for example, used as a memory in mobile devices.
From the initial discussion it becomes clear that, for example, newer devices cannot be expected as being compatible with legacy systems due to higher operating voltages used in legacy systems.
In view of the aforesaid, it is desirable to provide a semiconductor device structure that is compatible with different systems and/or that may be used as an interface between advanced computational systems and legacy systems. Furthermore, it is desirable to provide semiconductor device structures with co-integrated devices supporting different operating voltages.